A list of archectures that DO NOT use 'jmp' as unconditional jumps:-
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( From Google Gemini... )

  Here are the major CPU architectures that do not use the jmp mnemonic,
  along with the actual instructions they use instead...

  ARM (AArch32 / AArch64):-
  What it uses instead: B (Branch) or BR (Branch to Register).
  Why: ARM terminology uses "Branching" rather than "Jumping" for controlling
  program flow.

  MIPS:-
  What it uses instead: J (Jump), JR (Jump Register), or JAL (Jump and Link).
  Why: MIPS assembly language strictly standardises on single-letter
  mnemonics for its primary jump instructions.

  RISC-V:-
  What it uses instead: JAL (Jump and Link) or JALR (Jump and Link Register).
  Why: RISC-V optimizes its instruction set by using a single hardware
  instruction for both regular jumps and function calls. To perform a plain
  unconditional jump, software uses the pseudo-instruction j, which the
  assembler automatically translates into jal x0, offset.

  PowerPC / POWER:-
  What it uses instead: B (Branch), BL (Branch Linked), or BCTR (Branch to
  Count Register).
  Why: Like ARM, IBM's PowerPC architecture treats all jumps as branches.

  SPARC:-
  What it uses instead: BA (Branch Always) or JMPL (Jump and Link).
  Why: SPARC utilizes a "Branch Always" instruction for local jumps,
  reserving JMPL for register-based jumps and function returns.

  Alpha (DEC):-
  What it uses instead: BR (Branch) or JMP is technically used as a generic
  mnemonic but is represented in hardware as JSR (Jump to Subroutine) with a
  zeroed-out return address register.

  AVR (Atmel / Microchip):-
  What it uses instead: RJMP (Relative Jump) or IJMP (Indirect Jump).
  Why: While some larger AVR chips do feature a standard JMP instruction for
  flat 22-bit memory spaces, smaller AVR microcontrollers completely lack it
  to save silicon space, relying entirely on relative jumps.

