AminetAminet
Search:
83663 packages online
About
Recent
Browse
Search
Upload
Setup
Services

util/sys/FastCache040+.lha

Mirror:Random
Showing:m68k-amigaosppc-amigaosppc-morphosi386-arosi386-amithlonppc-warpupppc-powerupgeneric
No screenshot available
Short:Patch to replace CachePreDMA/CachePostDMA
Author:"SpeedGeek"
Uploader:polluks+aminet sdf lonestar org (Stefan Haubenthal)
Type:util/sys
Version:1.9
Requires:68040 or 68060 CPU and MMU
Architecture:m68k-amigaos
Date:2018-05-22
Download:http://aminet.net/util/sys/FastCache040+.lha - View contents
Readme:http://aminet.net/util/sys/FastCache040+.readme
Downloads:623

FastCache040+ 1.9 ©SpeedGeek 2018

INTRODUCTION:
FastCache040+ is a patch to replace the CachePreDMA() and
CachePostDMA() functions of most 68040/060 libraries. While
the old functions are adequate they are far from optimal.
These old functions have 2x more code then the new ones
provided with this patch!

Also, the new functions implement a much more efficient method
of managing the Copyback cache for DMA. While every system
will have some CPU performance loss under DMA conditions, the
new functions keep this performance loss to a bare minimum.

FEATURES:
- Replaces CachePreDMA() and CachePostDMA() with smaller
  and more efficient code
- Replaces complex MMU code with simple and fast DTTR code
- Temporarily changes Copyback mode to Write Through for DMA
  (but only when required!). See MEMF_24BIT change for v1.3.
- Never flushes the ATC!
- Never flushes the DC for Chip RAM DMA!
- Uses 68040/060 library detection code
- Will not patch itself
- 100% Assembler code

CODE SIZE COMPARISONS:
- FastCache040+ 1.9  (NewFunc 164 bytes)
- 68060.library 46.7 (OldFunc 304 bytes)
- 68040.library 44.2 (OldFunc 414 bytes)

REQUIREMENTS:
- Amiga with 68040 or 68060 CPU and MMU
- 68040.library or 68060.library

DISCLAIMER:
Use at your own risk. No warranty expressed or implied, etc.

DISTRIBUTION:
This program is freely distributable but must include this
text file.

USAGE:
- Copy FastCache040 into your C: directory
- Execute it from the shell or...
- Add it to your startup-sequence (Must be AFTER Setpatch!)
- If the install is successful the return code = 0
- If the install is NOT successful the return code = 5

WARNING:
Do NOT use this patch with GigaMEM, VMM or any similar
virtual memory software! Do NOT use this patch with any
code which uses the MMU to write protect or remap modified
data structures!

NOTES:
Remapping a mirror image of the Kickstart ROM with the MMU
is OK! The new functions still have one thing in common with
the old functions. They do NOT translate virtual addresses
as specified in the Amiga RKRM! For more info on the old
functions see the Enforcer.guide by Michael Sinz.

UPDATE:
FastCache040+ v1.7 has been removed. Phase5 68060.library
users should use FixMapP5 before using this patch.

HISTORY:
v1.0 - First release
v1.1 - Fixed a bug which prevented the patch from installing
     - Added code to use OldCachePreDMA for MEMF_24BIT
       transfers (I don't know why errors occured here)
v1.2 - Added code to use OldCachePostDMA for MEMF_24BIT
       transfers (So MMU Pages can be restored to original)
v1.3 - Added code to change MEMF_24BIT transfers to NoCache.
       This eliminated all OldFunc calls. MEMF_24BIT
       transfers may have some CPU performance loss but the
       NewFunc code performance benefits should still justify
       this.
v1.4 - Removed MEMF_24BIT code from PreDMA/PostDMA for the
       case of 16 byte aligned transfers. This will allow
       some MEMF_24BIT transfers to be cache enabled!
v1.5 - Found an occasional Recoverable Alert bug which could
       possibly result in a crash but only on 060 systems!
       The simple fix was to move "CINVA NC" in PostDMA to the
       end of the code.
     - Removed the "+" character from the executable name due
       to a unknown "Feature" of the Amiga Shell causing script
       execution and version command problems.
v1.6 - Added code to PostDMA to Flush the cache conditionally
       (if the Store buffer and cache are enabled). Added NOPs
       to sync the pipelines before RTE (CINVA is now obsolete).
v1.6P5 Removed code to allow PostDMA cache Flush for the case of
       16 byte aligned transfers. Added code to skip PostDMA
       cache Flush for the case of cache disabled MEMF_24BIT
       transfers.
v1.7 - Removed all v1.6P5 PostDMA cache flush code so users can
       run at full speed!
v1.8 - Reworked the code to eliminate a serious (but seldom
       noticed) data transfer corruption bug for the case
       of multiple DMA drivers in the same system. Special
       Thanks to Ralph Babel for his excellent knowledge on
       this topic.
v1.9 - Fixed "D2 Register Not Preserved" coding bug in PreDMA.
       Most DMA drivers don't seem to need it preserved but
       Thanks to Cosmos for reporting it anyway. Moved PostDMA
       Nest count code to user section of code. This eliminates
       any calls to Supervisor when the count is more than 1.


Contents of util/sys/FastCache040+.lha
PERMISSION  UID  GID    PACKED    SIZE  RATIO METHOD CRC     STAMP     NAME
---------- ----------- ------- ------- ------ ---------- ------------ ----------
[generic]                  335     408  82.1% -lh5- a8c8 May 20  1980 FastCache040
[generic]                 2072    4520  45.8% -lh5- 4abd May 20  1980 FastCache040+.txt
[generic]                  549    1365  40.2% -lh5- 8bd1 May 20  1980 NewFuncSrc/NewFunc.asm
---------- ----------- ------- ------- ------ ---------- ------------ ----------
 Total         3 files    2956    6293  47.0%            May 22 19:50

Aminet © 1992-2021 Urban Müller and the Aminet team. Aminet contact address: <aminetaminet net>